`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/07/14 12:08:15
// Design Name: 
// Module Name: MEM_WB
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module MEM_WB(
    input rst,
    input clk_i,
    input WB,
    input [1:0] WDSel,
    input [31:0] ALUd,
    input [31:0] DMd,
    input [31:0] rD2,
    input [31:0] imm,
    input [31:0] pc4,
    input [4:0] wR,
    output reg WB_out,
    output reg [1:0] WDSel_out,
    output reg [31:0] ALUd_out,
    output reg [31:0] DMd_out,
    output reg [31:0] rD2_out,
    output reg [31:0] imm_out,
    output reg [31:0] pc4_out,
    output reg [4:0] wR_out
    );
    
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      wR_out<=5'b0;
            else            wR_out<=wR;      
        end
    
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      WDSel_out<=2'b0;
            else            WDSel_out<=WDSel;      
        end
    
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      WB_out<=1'b0;
            else            WB_out<=1'b1;      
        end
        
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      ALUd_out<=32'b0;
            else            ALUd_out<=ALUd;      
        end
        
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      DMd_out<=32'b0;
            else            DMd_out<=DMd;      
        end
        
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      rD2_out<=32'b0;
            else            rD2_out<=rD2;      
        end
        
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      imm_out<=32'b0;
            else            imm_out<=imm;      
        end
        
    always @(posedge clk_i or posedge rst)
        begin
            if(rst)      pc4_out<=32'b0;
            else            pc4_out<=pc4;      
        end
endmodule
